Design and implementation of an ECG readout circuit based on advanced CMOS operational floating current conveyor /

Abstract

Portable medical equipment like heart rate, blood pressure and glucose monitors has become a common accessory. This led to a rise in need for low power single ended supply analog frontend biosensor circuits. They are required to operate from a single battery and occupy as small area as possible. In this thesis a few of those techniques are analyzed to find the most suitable for an Electrocardiogram (ECG) readout circuit. An ECG readout circuit consists of a low noise Instrumentation Amplifier (INA) to amplify the weak ECG signal followed by an Analog to Digital Converter (ADC) for processing or viewing on oscilloscopes and a couple of filters. The entire chip is based on the Operational Floating Current Conveyor (OFCC), which is a versatile analog building block capable of achieving most functions the Operational Amplifier (opamp) can realize with fewer external components. In this thesis, implementation of an ECG frontend based on the OFCC is presented and discussed. This implementation lead to a very small chip area compared to other designs in the literature. A low noise INA is constructed using 2 OFCC to amplify the signal with chopper technique to reduce flicker noise to 3 µVrms for bandwidth 0.05 – 100Hz for monitoring applications and 3.7 µVrms for bandwidth 0.05-150 Hz for diagnostic purposes. The high pass filter is constructed using a pseudo resistor. The ADC is a first order continuous time Sigma Delta Modulator (∑∆ ADC) with Oversampling Ratio (OSR) 128 equivalent to sampling frequency of 38.4 kHz. The ECG signal bandwidth is at most 150 Hz thus the 38.4 kHz sampling frequency is sufficient to achieve a resolution of 8 bits. The fully integrated overall chip area is merely 0.3 mm2. The area could be reduced to 0.078 mm2 by using an external capacitor for the ADC. Powered by a 0.4 V supply the circuit consumes 28.5 µW.